A three-dimensional integrated semiconductor circuit device in which a plurality of semiconductor chips are stacked on a semiconductor substrate is known (see, e.g., Patent Literature 1). This three-dimensional integrated semiconductor circuit device is manufactured by stacking a plurality of semiconductor chips on a first main surface of the semiconductor substrate and thinly grinding the semiconductor substrate from the second main surface side thereof.
For manufacturing, recessed parts are provided on the first main surface of the semiconductor substrate first, and conductive portions are formed in the recessed parts. Then a plurality of semiconductor chips are stacked on the first main surface of the semiconductor substrate. An encapsulation material is in turn injected in the space around the semiconductor chips. After the three-dimensional structure is formed in this manner, the semiconductor substrate is thinned from the second main surface side until the conductive parts penetrate to the second main surface.    [Patent Literature 1] Unexamined Japanese Patent Application KOKAI Publication 2005-51150